VHDL Language Specification

Commissioned by the United States Department of Defense in 1983, VHDL stands for VHSIC Hardware Description Language (where VHSIC stands for Very High Speed Integrated Circuit). It was initially created as a formal documentation language to describe how custom microchips behaved on military weapon platforms.

VHDL requires strict isolation between the structural interface of a block and its actual internal working mechanisms. Every design unit must include an explicit entity block defining input/output configurations, followed by an architecture layout definition describing internal data operations.

Example Project: 4-Bit Binary Up-Counter

The code block below outlines the exact same 4-bit synchronisation counter task implemented with formal VHDL formatting:

-- VHDL implementation for an asynchronous-reset up-counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vhdl_binary_counter is
port(C, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end vhdl_binary_counter;
architecture bhv of vhdl_binary_counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin
if (CLR=’1′) then
tmp <= "0000";
elsif (C’event and C=’1′) then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end bhv;

Execution Architecture

While the syntax is considerably more verbose than the Verilog model, the strong compilation system rules out data mismatch errors before you even attempt to upload the bitstream file onto the physical silicon chip. Once synthesised, both files yield identical physical layout gates inside the array logic cells.