Verilog Language Specification

Introduced in 1984 by Gateway Design Automation, Verilog was developed to make digital logic simulation cleaner and faster. Because its syntax shares structural similarities with the C programming language, software developers often find it more approachable than other engineering syntaxes.

Verilog operates on a module-based structure. Everything is defined within a module/endmodule block, inside which inputs, outputs, structural wires, and registers are defined explicitly.

Example Project: 4-Bit Binary Up-Counter

The code block below demonstrates a fully operational, asynchronous 4-bit register counter. This circuit checks for the rising edge of a system clock pulse and increments an unsigned integer tracking value accordingly:

// Verilog implementation for an asynchronous-reset up-counter
module counter(
    input clk,
    input rst,
    output [3:0] q
    );
     
    // counter register
    reg [3:0] rCounter;
     
    // increment or reset counter
    always @(posedge clk, posedge rst)
        if (rst)
            rCounter <= 0;
        else
            rCounter <= rCounter + 1;
 
    // connect counter register to output wires
    assign q = rCounter;
endmodule

Execution Architecture

Inside the silicon block, the synthesis engine parses the always @(posedge clk) block to realize that a physical latching mechanism is needed. Rather than executing lines of calculation sequentially, the physical circuit scales or clears its outputs simultaneously on the absolute edge of the clock signal line transition.